**Name of the Lab with Code: EE 232 Digital Circuits and Lab**

##### Syllabus:

- Review of basics of digital electronics: Number systems, Boolean algebra, logic gates and circuits, minimization of logic functions. Number representation and arithmetic circuits: Signed and unsigned numbers, binary codes, arithmetic operation of binary numbers-addition, subtraction and multiplication. Combinational circuit elements: Multiplexers and demultiplexers, decoders and encoders, code converters. Synthesis of combinational logic functions. Cyclic and acyclic logic circuits. Memory elements: latches and flipflops, applications-shift registers and counters. Sequential circuits and finite state machines: analysis and synthesis. Synchronous and asynchronous sequential circuits. Timing analysis of clocked circuits. Hazards in digital circuits. Transistor level implementation of digital circuit elements: CMOS digital family. Introduction to VHDL and programmable logic devices. Advanced digital system design topics and applications.

List of Experiments:

**Experiment 1: Two input OR gate**(This simple experiment is to get the students familiarized with the Quartus Prime Lite and Modelsim software as well as the Quartus design flow and DE10 Lite board.)**Experiment 2: Package and XOR gate (**This experiment is to get familiarized with VHDL package and make the students proficient with the Quartus design flow and DE10 Lite board.)**Experiment 3: Nibble Adder (**VHDL description for the HALF ADDER, FULL ADDER and NIBBLE ADDER using structural coding)**Experiment 4: Multiplexers (**VHDL description for the 2:1,4:1,1:2 and 1:4 multiplexer and demultiplexer using structural coding)**Experiment 5: Array Multiplier (**structural VHDL description of a 4-bit array multiplier for unsigned numbers**)****Experiment 6: Code Converters (**- Design an adder/subtractor unit that operates on two 4-bit XS3 encoded operands and gives out an 8-bit BCD encoded output.
- Design a BCD to seven-segment display code converter and observe the outputs on the SSD panel on the FPGA board.
- Combine the above designs to show the sum/difference using seven-segment displays and demonstrating the functionality on a DE10 Lite board.

**Experiment 7: Arithmetic Logic Unit (**Design an ALU which performs the eight arithmetic and logic operations such as addition, subtraction, multiplexing, multiplication, etc. and demonstrate the functionality on a DE10 Lite board.)**Experiment 8: Asynchronous Sequential Circuits**- VHDL description for the entity of a positive level triggered D latch
- VHDL description for the entity of a positive edge triggered D flipflop with Active low clear and preset input
- Design a clock divider that generates a 1 Hz clock from the 50 MHz internal clock available on the DE10 Lite board.
- Design of a four-bit asynchronous up/down counter with a global asynchronous reset input. The counter should count up if the UP/DN signal is high and count down if it is low. The counter output should change in every second. When the active low RSTN signal is asserted, the counter should reset immediately to 0000 if the UP/DN signal is high and to 1111 if the UP/DN signal is low.
- Demonstrate the functionality on a DE10 Lite board.

**Experiment 9: Synchronous Sequential Circuits**- Design a synchronous BCD up/down counter with a global synchronous reset input. The counter should count up (0 to 9) if the UP/DN signal is high and count down (9 to 0) if it is low. The counter output should change in every second. When the active low RSTN signal is asserted, the counter should reset to 0000 if the UP/DN signal is high and to 1001 if the UP/DN signal is low. The counter should load the value D when the LDN signal is asserted. There should also be a global enable signal to the counter.
- Instantiating the same counter, design a two-digit counter and showing the output on two seven segment displays of a DE10 Lite board.

**Experiment 10: Finite State Machines**- Design Moore type and Mealy type finite state machines for specified functionality
- Demonstrate the functionality on a DE10 Lite board.

**Experiment 11: Tone Generator**This Experiment is to generate musical notes such as Sa Re Ga … and generate melodies using them with the help of a DE10 Lite board

References:

- Stephen Brown and Zvonko Vranesic, “Fundamentals of Digital Logic with VHDL Design,”
*Tata McGraw Hill* - John F. Wakerly, “Digital Design: Principles and Practices,”
*Pearson Education India*

Charles H. Roth Jr. and Larry L. Kinney, “Fundamentals of Logic Design,”*CL-Engineering* - Perry D. L., “VHDL: Programming by Example,”
*Tata McGraw Hill* - Zvi Kohavi and Niraj K. Jha, “Switching and Finite Automata Theory,”
*Cambridge University Press* - M. Morris Mano and Michael D. Ciletti, “Digital Design: With an Introduction to the Verilog HDL,”
*Pearson Education India*

### Lab sessions:

- We will be using Quartus and Modelsim for VHDL programming and simulationWho are going to help us?