ABOUT

Dr. Sudakshina Datta (Photo)

Dr. Sudakshina Dutta

Assistant Professor

Computer Science and Engineering

Research Interests : Formal Verification, Static analysis

sudakshina[at]iitgoa[dot]ac[dot]in

F9, Room No. 205, IT Building,IIT Goa, Farmagudi, Ponda-403401, Goa, India

0832-2490-126

Publications

EDUCATION

APPOINTMENTS

  1. Assistant Professor in IIT Goa.
  2. Interra Systems
    Designation: Member of Technical Staff
    Area : Developer of hierarchical integrated circuit mask layout data reader and writer libraries
    Duration: July 2007 - July 2009

TEACHING

AUTUMN 2019

  1. CS302 Introduction to Compilation Techniques
  2. CS306 Introduction to Compilation Techniques laboratory
  3. CS102 Software Systems Laboratory

SPRING 2020

  1. CS511 Approaches to software performance enhancement

AUTUMN 2020

  1. CS228 Logic in Computer Science

SPRING 2021

  1. CS302 Introduction to Compilation Techniques
  2. CS306 Introduction to Compilation Techniques laboratory

PUBLICATIONS

CONFERENCES

  1. Validation of Loop Parallelization and Loop Vectorization Transformations
    Sudakshina Dutta, Dipankar Sarkar, Arvind Rawat, Kulwant Singh
    11th International Conference on Evaluation of Novel Approaches to Software Engineering (ENASE) 2016, Rome, Italy, April, 2016.
  2. An Enhanced Equivalence Checking Method to Handle Bugs in Programs with Recurrences
    Sudakshina Dutta, Dipankar Sarkar
    11thInternational Conference on Evaluation of Novel Approaches to Software Engineering (ENASE) 2016, Rome, Italy, April, 2016.
  3. A Cognitive Approach to Word Sense Disambiguation. Sudakshina Dutta, Anupam Basu 13th International Conference, CICLing 2012, New Delhi, India, March, 2012.

JOURNALS

  1. Synchronization Validation for Cross-Thread Dependences in Parallel Programs.
    Sudakshina Dutta, Dipankar Sarkar, Arvind Rawat
    International Journal of Parallel Programming (IJPP), accepted(2016).
  2. Validation of parallelizing transformations of sequential programs.
    Sudakshina Dutta Concurrency and Computation: Practice and Experience (CPE), vol. 29, no. 8, 2017.

POSTERS

  1. Validation of Loop Concurrentization Transformations for Sequential Programs.
    Sudakshina Dutta, Dipankar Sarkar, Arvind Rawat
    IMPECS-POPL Workshop on Emerging Research and Development Trends in Programming Languages (WEPL), Mumbai, India, 2015.

RESEARCH

  1. Formal Verification
  2. Program Analysis
  3. Compiler Technologies


PROJECT

A JRF (PhD position) against SERB Power grant is available. The summary of the project is given below.

Summary: Software failures are very common and fault localization is always an important, but laborious activity. In practice, developers are aware of the number of failed test cases for their programs, but they are unaware of whether a single fault or many faults caused those failures. Generally, developers start with one fault at a time and they consider a single test case to find the cause of failures. After a fault is found and fixed, the program is tested again to determine whether the previously failing test case now passes. If any further failure is found, the debugging process is conducted again. This process is called sequential debugging in literature. It is a time-consuming process and requires a set of test cases indicating presence of each of the faults. Sometimes, the presence of multiple faults in a program inhibits the ability of the fault localization techniques as certain faults mask other faults. In absence of appropriate test cases, some faults may remain unidentified for years.

This project aims to eliminate the need of test cases and the need for repeated invocation of the fault localization method. In model-based fault localization methods, the correct model of each program being diagnosed is assumed to be available. In general, these techniques require test cases and user-specified assertions to localize the fault. The aim of the proposal is to project a model-based fault localization method which takes the correct and the faulty programs as inputs. It would indicate the code segment responsible for fault in the faulty program with respect to the correct program for every fault and the method would not require user-specified assertions or test cases.


If you are interested in applying, please send an email to me or submit your interest below    
If you are interested in applying, please send an email to me or submit your interest below.
Please follow the eligibility criteria given in the page 6 of the link : LINK